Design of 16 - bit Reversible Logic Carry Look Ahead Adder Circuit

RTL View of a single 4 - bit Reversible CLA

RTL View of the Entire 16 - bit Reversible Logic CLA

Logical Verification Using ModelSim - Altera

Energy is dissipated whenever a bit of information is destroyed. Today's Digital Systems are based on irreversible logic wherein the input cannot be determined from the output. As a consequence there is a loss of information. This loss of information corresponds to dissipation of energy.

Reversible Logic Gates

 

Reversible Computers have a one-to-one and onto mapping between the input and output logic. This means that each of the input is mapped to a unique output. Therefore, the operations can be un-computed. In a reversible system, overwriting operations are avoided.

In this Mini-Project I have designed and simulated a 16 - bit Logically Reversible Carry Look Ahead Adder using Intel Quartus Prime.

Compilation Result

 

Verilog HDL is used for the Design entry.  

ModelSim - Altera for the Logical Verification.

Reversible Logic Gates Used: Peres Gate, Fredkin Gate

Drop Comments if you want access to the HDL files.